Modeling and Analysis of Distributed Reconfigurable Hardware∗
نویسندگان
چکیده
The ability to migrate hardware processes in a network of hardware reconfigurable nodes improves the fault tolerance of these networks. The degree of fault tolerance is inherent to such networked systems and can be optimized during design time. Therefore, an efficient way of calculating the degree of fault tolerance is needed. This paper presents an approach based on satisfiability testing which regards the question: How many resources may fail in a distributed reconfigurable system without losing any functionality?
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تاریخ انتشار 2004